Inverse tone direct print euv lithography enabled by selective material deposition

ABSTRACT

Various methods and structures for fabricating a plurality of vertical fins in a vertical fin pattern on a semiconductor substrate where the vertical fins in the vertical fin pattern are separated by wide-open spaces, along a critical dimension, in a low duty cycle of 1:5 or lower. Adjacent vertical fins in the vertical fin pattern can be all separated by respective wide-open spaces, along a critical dimension, in a low duty cycle, and wherein pairs of adjacent vertical fins in the vertical fin pattern, along the critical dimension, are separated by a constant pitch value at near zero tolerance.

BACKGROUND

The present invention generally relates to the field of semiconductors,and more particularly relates to a method of fabricating fin structuresthat form the semiconducting channel in vertical transistor structures,fin field-effect-transistor (finFET) structures, BEOL verticalmetallization structures, and the like, on semiconductor chips.

Fin field-effect transistor (finFET) devices include a transistorarchitecture that uses raised source-to-drain channel regions, referredto as fins. A finFET device can be built on a semiconductor substrate,where a semiconductor material, such as silicon, is patterned into afin-like shape and functions as the channel of the transistor. KnownfinFET devices include fins with source/drain regions on lateral sidesof the fins, so that current flows in a horizontal direction (e.g.,parallel to the semiconductor substrate) between source/drain regions atopposite ends of the fins in the horizontal direction.

Very recently, chip designs have started to use vertical field-effecttransistors to help increase the number of transistors that can fit on achip without having to substantially increase the overall chip size. Forexample, by using vertical transistor structures, it can increase the onchip finFET-equivalent density along a plane parallel to thesemiconductor substrate. Vertical transport architecture FET devicesinclude source/drain regions at ends of the fins on top and bottom sidesof the fins so that current flows through the fins in a verticaldirection (e.g., perpendicular to the semiconductor substrate) between abottom source/drain region and a top source/drain region.

As chip designs continue to further miniaturize on-chip devicedimensions, such designs attempt to locate vertical FETs closer andcloser to each other on a semiconductor chip to enhance the featuredensity. The distance between a feature on a fin and the same feature onan adjacent fin is the pitch of the pattern of fins on a chip. Asvertical FETs are located closer to each other, the respective fins ofadjacent vertical FETs are separated from each other by smaller pitchvalues and tighter pitch tolerances (pitch variability), to meet chipdesign requirements. As pitch values between adjacent fins becomesmaller, conventional fabrication chronologies such as 193i opticallithography concede that a single lithographic exposure (also referredto as “direct print” lithography) is not capable of providing sufficientresolution in order to meet the higher feature density requirements.

Conventional semiconductor fabrication processes have attempted toenhance the feature density by using fabrication technologies thatinvolve multiple-patterning (or multi-patterning) such as Self-AlignedDouble Patter g (SADP), and Self-Aligned Quadruple Patterning (SAQP).The minimum pitch for a single 193i optical lithographic exposure isrecognized to be limited to 76 nm. SADP and SAQP techniques utilizemultiple depositions and etch processes, to attempt to increase thefeature. For example, with the SAQP technique a 19 nm pitch (i.e., 76 nmdivided by 4) is now accessible in principle.

Process variability in the multiple patterning processes leads to errorssuch as pitch-walk, which are excursions of the pitch from the nominalvalue. Pitch walk can also accumulate tolerance errors over multiplesequential pairs of adjacent fins.

Though state-of-the-art direct print lithography techniques (directprint lithography, inherently has zero pitch walk) such as extremeultra-violet (EUV) lithography (13.5 nm wavelength) can pattern muchsmaller pitches than the 76 nm achievable by 193i optical lithography,there are still so e drawbacks such as the duty cycles for a givenprocess formulation. The term “duty cycle” defines the spacing betweenlines (features) relative to the width of the lines (features) in thecritical dimension, expressed as a ratio. Smaller duty cycles such as1:5 (line width of 1 part to a space width of 5 parts at pitches smallerthan 76 nm) are still a challenge to fabricate using any availabledirect print technology. That is, typical semiconductor fabricationapplications have been limited to regular width lines separated byspaces of regular width that is equal to the regular width of the lines(i.e., a 1:1 duty cycle).

Therefore, the inventors have discovered that there is a need for a newfabrication method of semiconductor structures to fabricate patterns oflow duty cycle (thin lines flanked by large spaces) with zero toleranceon pitch variability (pitch walk).

SUMMARY OF THE INVENTION

Various embodiments of the present invention include fabrication ofvertical fins in a vertical fin pattern on a circuit supportingsubstrate. The vertical fins in the vertical fin pattern on the circuitsupporting substrate are separated by wide-open spaces, along a criticaldimension, in a low duty cycle of 1:5 or lower. According to certainembodiments, adjacent vertical fins in the vertical fin pattern can beall separated by respective wide-open spaces, along a criticaldimension, in a low duty cycle, and wherein pairs of adjacent verticalfins in the vertical fin pattern, along the critical dimension, areseparated by a constant pitch value at near zero tolerance.

A method and structure, for example, can form vertical transistors, finFET transistors, and back-end-of-line (BEOL) metallization structures onthe same chip. According to various embodiments, a method forfabricating a pattern of vertical fins in a semiconductor structure,comprises: providing a semiconductor material stack including aplurality of layers; and creating an inverse tone pattern in thesemiconductor material stack, where a critical dimension of the inversetone pattern is defined by selective sidewall atomic layer deposition tocreate trenches in at least one layer in the plurality of layers.

In one embodiment, a method for fabricating a pattern of vertical finsin a semiconductor structure, the method comprising: providing asemiconductor material stack including: a semiconductor substrate layer;a fin hard mask stack, including one or more layers, disposed on thesemiconductor substrate layer; a first material layer, consisting of afirst material, disposed on the fin hard mask stack; and aphotolithography stack, including one or more layers, disposed on thefirst material layer; and the method including: forming an inverse tonedirect print pattern on the photolithography stack; performing firstvertical directional etching in the photolithography stack and in thefirst material layer only where layers are vertically exposed outside ofthe inverse tone direct print pattern; removing, after the firstvertical directional etching, the photolithography stack to form amandrel pattern in the first material layer disposed on the fin hardmask stack; performing selective sidewall spacer deposition on sidewallsof the mandrel pattern in the first material layer, to form trenchesbetween sidewall spacers that were selectively deposited on thesidewalls of the mandrel pattern; performing selective bottom-up trenchfill with a second material to fill only the trenches that were formedbetween sidewall spacers; performing etching to remove the mandrel andthe sidewall spacers, leaving the second material disposed, in a firstpattern following a pattern of the trenches that were formed betweensidewall spacers, on the fin hard mask stack; performing second verticaldirectional etching in the fin hard mask stack and in the semiconductorsubstrate layer only where layers are vertically exposed outside of thefirst pattern of the second material disposed on the fin hard maskstack, to form vertical fins in a vertical fin pattern in thesemiconductor substrate layer; and removing, after the second verticaldirectional etching, the second material and the fin hard mask stack,exposing the vertical fins in the vertical fin pattern formed in thesemiconductor substrate layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying figures where like reference numerals refer toidentical or functionally similar elements throughout the separateviews, and which together with the detailed description below areincorporated in and form part of the specification, serve to furtherillustrate various embodiments and to explain various principles andadvantages all in accordance with the present invention, in which:

FIG. 1 is a cross-sectional side view of an example of a partialsemiconductor structure illustrating a material stack that can be usedin an example fabrication process, according to an embodiment of thepresent invention;

FIG. 2 is a cross-sectional side view of the partial semiconductorstructure of FIG. 1 at a point in the example fabrication processfollowing patterning and etching of the material stack, such as forfabricating finFET semiconductor devices, according to an embodiment ofthe present invention;

FIG. 3 is a cross-sectional side view of the partial semiconductorstructure of FIG. 2 at a point in the example fabrication processfollowing removal of a portion of the material stack and formation of amandrel pattern on top of the remaining material stack;

FIG. 4 is a cross-sectional side view of the partial semiconductorstructure of FIG. 3 at a point in the example fabrication processfollowing selective sidewall spacers deposition on the sidewalls of themandrel pattern and defining trenches with the spacers, according to anembodiment of the present invention;

FIG. 5 is a cross-sectional side view of the partial semiconductorstructure of FIG. 4 at a point in the example fabrication processfollowing selective material deposition in the trenches, according to anembodiment of the present invention;

FIG. 6 is a cross-sectional side view of the partial semiconductorstructure of FIG. 5 at a point in the example fabrication processfollowing etching removal of the mandrel pattern and the spacers,leaving an inverse tone pattern of the material deposited in thetrenches in FIG. 5 on top of the remaining material stack, according toan embodiment of the present invention;

FIG. 7 is a cross-sectional side view of the partial semiconductorstructure of FIG. 6 at a point in the example fabrication processfollowing etching removal of a portion of the remaining material stackto form a pattern of fins on the semiconductor substrate, according toan embodiment of the present invention;

FIG. 8 shows Table 1, illustrating examples of materials in Table 1 withreference to a cross-sectional side view of the example partialsemiconductor structure shown in FIG. 5, according to an embodiment ofthe present invention; and

FIG. 9 is an operational flow diagram illustrating an example processfor fabricating vertical finFET devices on a circuit supportingsubstrate, according to an embodiment of the present invention.

DETAILED DESCRIPTION

It is to be understood that the present invention will be described interms of illustrative example processes for fabricating finFETsemiconductor devices and vertical transistor semiconductor devices.However, other semiconductor architectures, structures, substratematerials, and process features and steps may be varied within the scopeof the present invention. The terms “pitch walk”, “pitch variability”,“pitch tolerances”, and the like, synonymously mean herein the same typeof semiconductor structure metrology to determine pitch values ofadjacent fin structures in a pattern of fins disposed on a semiconductorsubstrate. These patterns of fins may be used, for example, to fabricatefin structures for one or more of: finFET semiconductor devices,vertical transistor semiconductor devices, vertical metallizationstructures in the back-end-of-line (BEOL) metallization layers, and thelike.

The term “duty cycle” as used herein is defined as the spacing betweenlines (e.g., features such as fins) relative to the width of the lines(features such as fins) in the critical dimension, expressed as a ratio.That is, for example, adjacent fins have a first width, in a criticaldimension, and these adjacent fins are separated by a space having asecond width, in the critical dimension. When the first width equals thesecond width, the duty cycle is 1:1. As a second example, when thesecond width (the width of the space) is twice the first width (thewidth of each of the adjacent fins), the duty cycle is 1:2. A duty cycleof 1:2 is smaller than a duty cycle of 1:1. The terms “small duty cycle”or “low duty cycle” synonymously mean herein a duty cycle ofsubstantially 1:5 or smaller.

It will also be understood that when an element such as a layer, regionor substrate is referred to as being “on” or “over” another element, itcan be directly on the other element or intervening elements may also bepresent. Similar but inverse meaning will be understood for an elementsuch as a layer, region, or substrate that is referred to as being“under” or “below” another element. It can be directly under the otherelement or intervening elements may also be present. In contrast, whenan element is referred to as being “directly on” or “directly over”, oralternatively referred to as being “directly under” or “directly below”another element, there are no intervening elements present. It will alsobe understood that when an element is referred to as being “connected”or “coupled” to another element, it can be directly connected or coupledto the other element or intervening elements may be present. Incontrast, when an element is referred to as being “directly connected”or “directly coupled” to another element, there are no interveningelements present.

The present embodiments may include a design for an integrated circuitchip, which may be created in a graphical computer programming language,and stored in a computer storage medium (such as a disk, tape, physicalhard drive, or virtual hard drive such as in a storage access network).If the designer does not fabricate chips or the photolithographic masksused to fabricate chips, the designer may transmit the resulting designby physical means (e.g., by providing a copy of the storage mediumstoring the design) or electronically (e.g., through the Internet) tosuch entities, directly or indirectly. The stored design is thenconverted into the appropriate format (e.g., GDSII) for the fabricationof photolithographic masks, which typically include multiple copies ofthe chip design in question that are to be formed on a wafer. Thephotolithographic masks are utilized to define areas of the wafer(and/or the layers thereon) to be etched or otherwise processed.

Methods as described herein may be used as part of a process in thefabrication of integrated circuit chips. The resulting integratedcircuit chips can be distributed by the fabricator in raw wafer form(that is, as a single wafer that has multiple unpackaged chips), as abare die, or in a packaged form. In the latter case the chip is mountedin a single chip package (such as a plastic carrier, with leads that areaffixed to a motherboard or other higher level carrier) or in amultichip package (such as a ceramic carrier that has either or bothsurface interconnections or buried interconnections). In any case thechip is then integrated with other chips, discrete circuit elements,and/or other signal processing devices as part of either (a) anintermediate product, such as a motherboard, or (b) an end product. Theend product can be any product that includes integrated circuit chips,ranging from toys and other low-end applications to advanced computerproducts having a display, a keyboard or other input device, and acentral processor.

Reference in the specification to “one embodiment” or “an embodiment” ofthe present principles, as well as other variations thereof, means thata particular feature, structure, characteristic, and so forth describedin connection with the embodiment is included in at least one embodimentof the present principles. Thus, the appearances of the phrase “in oneembodiment” or “in an embodiment”, as well any other variations,appearing in various places throughout the specification are notnecessarily all referring to the same embodiment.

It is to be understood that the various layers and/or regions shown inthe accompanying drawings are not drawn to scale, and that one or morelayers and/or regions of a type commonly used in complementarymetal-oxide semiconductor (CMOS), fin field-effect transistor (finFET),metal-oxide-semiconductor field-effect transistor (MOSFET) and/or othersemiconductor devices may not be explicitly shown in a given drawing.This does not imply that the layers and/or regions not explicitly shownare omitted from the actual devices. In addition, certain elements maybe left out of particular views for the sake of clarity and/orsimplicity when explanations are not necessarily focused on the omittedelements. Moreover, the same or similar reference numbers usedthroughout the drawings are used to denote the same or similar features,elements, or structures, and thus, a detailed explanation of the same orsimilar features, elements, or structures will not be repeated for eachof the drawings.

The semiconductor devices and methods for forming same in accordancewith various embodiments of the present invention can be employed inapplications, hardware, and/or electronic systems. Suitable electronichardware and systems for implementing embodiments of the invention mayinclude, but are not limited to, personal computers, communicationnetworks, electronic commerce systems, portable communications devices(e.g., cellular and smart phones), solid-state media storage devices,functional circuitry, etc. Systems and hardware incorporating thesemiconductor devices and structures are contemplated embodiments of theinvention. Given the teachings of example embodiments of the inventionprovided herein, one of ordinary skill in the art will be able tocontemplate other implementations and applications of embodiments of theinvention.

Various embodiments of the present invention can be implemented inconnection with semiconductor devices, and related semiconductorfabrication processes, that may use CMOSs, MOSFETs and/or finFETstechnology. By way of non-limiting example, the semiconductor devicescan include, but are not limited to CMOS, MOSFET, and finFET devices,and/or semiconductor devices that use CMOS, MOSFET and/or finFETtechnology.

As used herein, “vertical” refers to a direction perpendicular to asubstrate in the cross-sectional and three-dimensional views herein.Current between source/drain regions can be described herein as flowingin a vertical direction (e.g., between a bottom source/drain region anda top source/drain region) through a fin channel region. As used herein,“horizontal” refers to a direction parallel to a substrate in thecross-sectional and three-dimensional views herein.

As used herein, “thickness”. “thick”, or the like, refers to a size ofan element (e.g., a layer, trench, hole, etc.) in the cross-sectionalviews measured from a bottom surface to a top surface, or from a leftside surface to a right side surface of the element, and/or measuredwith respect to a surface directly adjacent to and contacting theelement (e.g., a surface on which the element is directly disposed on).

Unless otherwise specified, as used herein, “height” or “height above asubstrate” refers to a vertical size of an element (e.g., a layer,trench, hole, etc.) in the cross-sectional views measured from a topsurface of the substrate to a top surface of the element. A thickness ofan element can be equal to a height of the element if the element isdirectly on the substrate.

As used herein, the terms “lateral,” “lateral side,” “lateral surface”refer to a side surface of an element (e.g., a layer, opening, etc.),such as a left or right side surface in the cross-sectional viewsherein.

As used herein, the terms “pitch” or “pitch value”, and the like, referto a distance from a point on a first fin structure to a correspondingpoint on a second fin, in a pattern of fin structures disposed on asemiconductor substrate. The points of reference may be located at astart point, at a center point, or at an endpoint, of a fin structureand a corresponding adjacent fin structure. For example, with referenceto FIG. 1, a pitch value 203 can be measured from a start point of afirst structure to a start point of an adjacent second structure. Pitchvalue measurements can be taken between the first and second structures,between the second and a third structure, between the third and a fourthstructure, and so forth. Additionally, the terms “width” or “widthvalue”, and the like, refer to a distance from a start point on a firststructure to an end point on the same structure, in a criticaldimension. For example, with reference to FIG. 1, a width value 205 canbe measured from a start point on a structure to an end point on thesame structure, in a critical dimension.

Various embodiments of the present invention include a plurality of finson the same semiconductor substrate on a wafer. This structure may beused, for example, to create CMOS devices in an integrated circuit.

Referring now to the drawings in which like numerals represent the sameor similar elements, FIG. 1 shows an example of a material stack 202,204, 206, 208, 210, 212, 214, 216, 218, suitable for fabrication of aplurality of vertical finFET devices. A semiconductor substrate layer218, for example, comprises silicon. However, other semiconductormaterials may be used according to various embodiments of the presentinvention. A pad oxide layer 216 is disposed on the silicon layersilicon layer 218, according to the present example. The pad oxide layer216, for example, is approximately 30 Å thick.

A fin hard mask stack 210, 212, 214, is disposed on the pad oxide layer216. The fin hard mask stack, according to the example, comprises asilicon nitride layer 210, optionally disposed on one or more layers212, 214. Additionally, while the present example fin hard mask stack210, 212, 214, includes three layers of the same material or ofdifferent materials, certain embodiments can include a different numberof layers of a fin hard mask stack. For example, a fin hard mask stackcould include four layers of the same material or of differentmaterials.

A first material layer 208 is disposed on top of the fin hard maskstack, e.g., disposed on the first silicon nitride layer 210 accordingto the present example. The first material 208, in this example,comprises silicon dioxide. It should be noted that the first material208, according to certain embodiments, could be a material other thansilicon dioxide. For example, in one embodiment the first material 208could be silicon nitride.

A photolithography stack 202, 204, 206, is disposed on top of the firstmaterial layer 208. The photolithography stack 202, 204, 206, mayinclude one or more layers. For example, a photolithography stack mayinclude, in certain embodiments, a first photolithography layer(photoresist layer) 202 disposed directly on a second photolithographylayer comprising SiARC (silicon containing anti-reflective coating) 204which is disposed directly on a third photolithography layer comprisingOPL (optical planarizing layer) 206.

An inverse tone direct print pattern is formed on the inverse tonedirect print layer (photoresist layer) 202. Inverse tone lithography isa direct print lithography process that, according to one example, mayuse extreme ultraviolet light (EUV). The direct print lithographyprocess can be, for example, any one of extreme ultra-violetlithography, 193i optical lithography, electron-beam lithography, ornanoimprint lithography.

In the final structure, it would be desirable to have element (line)widths as small as possible (thin lines) while increasing the spacing(wide-open spaces) between the elements (lines). However, such types ofstructures with low duty cycles, e.g., a duty cycle of 1:5 or lower,normally cannot be created using a direct print lithography process.Direct print lithography processes are typically used to createstructures at, or close to, a 1:1 duty cycle.

Referring to FIG. 2, a fabrication process performs a first verticaldirectional etch in the photolithography stack layers 204, 206, and inthe first material layer 208. An example of a vertical directionaletching process that etches into layer 204 is reactive ion etching (RIE)using a fluoride based chemistry. The first vertical directional etchingstep vertically etches only where the layers 204, 206, 208, arevertically exposed outside of the inverse tone direct print pattern inthe inverse tone direct print pattern layer (photoresist layer) 202. Thestructure is achieved by dry etching layer 204 using layer 202 as themask using a fluoride based chemistry. The layer 206 is etched usinglayers 202 and 204 as masks using an oxygen or nitrogen/hydrogen orhydrogen bromide based chemistry. During this etching process, layer 202is removed. Then layer 208 is etched using layers 204 and 206 as masksusing a fluoride chemistry while simultaneously removing layer 204.After the first vertical directional etching, the remaining layer of thephotolithography stack (OPL layer) 206, is removed from the etched firstmaterial layer 208 by using a dry etch process such as an oxygen plasma,as shown in FIG. 3. In another instance, material (OPL) 206 can beremoved by using a suitable wet-etchant.

The etched first material layer 208 comprises a mandrel pattern 402,404, 406, 408, with trenches 302, 304, 306, located where the firstmaterial layer 208 was etched. The semiconductor fabrication processcontinues, with reference to FIG. 4, by performing selective sidewallspacer deposition on sidewalls of the mandrel pattern 402, 404, 406,408. This can be done using a selective atomic layer deposition (ALD)process that deposits material only on materials 402, 404, 406, 408 andnot on the exposed material 210 in the trenches 302, 304, 306. Sidewallspacers 502, 504, are formed on the sidewalls of all of the mandrelpattern 402, 404, 406, 408, without depositing sidewall spacer materialat the bottom of the trenches 302, 304, 306, and without depositingsidewall spacer material on top of the first material 208 of the mandrelpattern 402, 404, 406, 408. After the selective sidewall spacerdeposition on the sidewalls of the mandrel pattern, there remain gaps inthe trenches 302, 304, 306, between the sidewall spacers 502, 504,formed on the sidewalls of all of the mandrel pattern. These gaps arenarrow trenches between the sidewall spacers 502, 504.

Referring to FIG. 5, the semiconductor fabrication process continues byperforming selective bottom-up trench fill with a second material 602that fills only the narrow trenches that were formed between thesidewall spacers 502, 504. The second material 602, according to theexample, comprises Transition Metal Oxides. It should be noted thatother types of materials may be used in the second material 602,according to various embodiments of the present invention. In theselective bottom-up trench fill process, the second material 602 is notdeposited on top of the mandrel pattern (comprising the first material)402, 404, 406, 408. The second material 602 selectively fills the narrowtrenches (e.g., the second material 602 grows and deposits only in thenarrow trenches) from the bottom of the trenches by using a cyclicalbottom up trench fill process. In this cyclical trench fill process, alayer of the second material 602 is selectively grown at the bottom ofthe narrow trenches. The layer of the second material 602 is thenvertically directionally etched and leveled from spacer to spacer 502,504, inside the narrow trenches. This cyclical trench fill process isrepeated by selectively growing another layer of the second material 602on top of the second material 602 previously deposited in the narrowtrenches, until the narrow trenches are filled with the second material602 to a desired level. By controlling the number of cycles used to growthe second material 602 in the narrow trenches, it in turn controls thethickness of the second material 602 in the narrow trenches.

An alternative fabrication process to the above described selectivebottom-up trench fill process, would fill up the narrow trench using adeposition technique such as atomic layer deposition (ALD) of a “thincoat material” used to fill up the trench, or by using chemical vapordeposition (CVD) to fill up the trench. This deposition of the secondmaterial in the narrow trench may result in an overflow of the secondmaterial above the trench. In such a case, a planarization such as by achemical and mechanical polishing (CMP) step or an etching step can beused to bring the level of the second material down to only fill thetrench.

The semiconductor fabrication process then continues, with reference toFIG. 6, by performing an etching process to remove the mandrel layer 208including removal of the sidewall spacers 502, 504. For example, a wetor dry etch process can be used to remove the first material 208 and thespacers 502, 504, deposited on it. This etching process leaves a firstpattern of wide-open spaces 702 between thin lines 602 comprising thesecond material 602. The thin lines 602 made of the second material, andseparated by the wide-open spaces 702, are disposed on top of the finhard mask stack 210, 212, 214. It should be noted that the first patternof the second material 602 is an inverse tone pattern of the pattern ofthe mandrel 402, 404, 406, 408, and the sidewall spacers 502, 504, shownin FIG. 4. That is, the pattern of the second material 602 shown in FIG.6 is the inverse of the pattern of the mandrel 402, 404, 406, 408, andsidewall spacers 502, 504, shown in FIG. 4. A suitable wet etch processthat is selective to material 602 is used to etch materials 402, 404,406, 408 along with the side wall spacers 502, 504.

With reference to FIG. 7, a second vertical directional etching isperformed in the fin hard mask stack 210, 212, 214, and in the oxide padlayer 216 and the semiconductor substrate layer 218. An example of avertical directional etching process is reactive ion etching (RIE). Thissecond vertical directional etching removes material from the layers210, 212, 214, 216, 218, only where the layers 210, 212, 214, 216, 218,are vertically exposed outside of the first pattern of the secondmaterial 208, disposed on the fin hard mask stack 210, 212, 214. Thesecond material 602 is then removed leaving the fin hard mask stacks 801on fin structures 802, 804, 806, 808. Wide-open spaces 702 have beenformed between the fins 802, 804, 806. 808. The width of the spaces 702,along a critical dimension, is much greater than the width of the lines(fins 802, 804, 806. 808), also along the critical dimension, resultingin a low duty cycle of 1:5 or lower. As a subsequent step in thissemiconductor fabrication process, the fin hard mask stack 210, 212,214, and the pad oxide 216, are removed by etching. A suitable wet etchprocess that is selective to the silicon substrate (218) is used to etchthe fin hard mask stack 801.

The fins 802, 804, 806. 808, in the semiconductor substrate layer 218provide the structure for fabricating, for example, verticaltransistors, finFETs, and vertical metallization in a BEOL stack of oneor more layers of metallization. Additionally, because direct printphotolithography is used in this semiconductor fabrication process thepitch of the fins 802, 804, 806, 808, in a pattern on the substrate 218can be designed and fabricated to a near zero tolerance (near zerovariability). That is, for example, a first pitch between a first fin802 and a second fin 804, along a critical dimension, is equal to (ornearly equal to within negligible tolerances of lower than 0.1 nm) asecond pitch between the second fin 804 and a third fin 806, along thecritical dimension. This second pitch is equal to a third pitch betweenthe third fin 806 and a fourth fin 808, along the critical dimension.This third pitch is equal to a fourth pitch between the fourth fin 808and a subsequent structure 810, along the critical dimension.

A semiconductor structure design, according to an embodiment of thepresent invention, has a significant advantage of providing acombination of low duty cycle (i.e., a duty cycle of 1:5 or lower) witha fin pattern 802, 804, 806, 808, having zero pitch walk (or nearly zeropitch walk within negligible tolerances of lower than 0.1 nm). By nearlyzero pitch walk within negligible tolerances, it is intended to meanthat the variability in pitch between pairs of fins along a criticaldimension will be zero or a variability that is of no consequence to adesign relying on zero pitch walk. For example, and not for limitation,a low duty cycle with zero pitch walk (e.g., pitch variability) designcould be fabricated to a maximum tolerance of less than one tenth of ananometer. This new semiconductor structure design and associatedfabrication methods for direct print patterning of low duty cyclestructures, as discussed herein, have not been possible until thepresent invention.

FIG. 8 shows Table 1 which provides various examples of the firstmaterial 208, the sidewall spacer material 502, 504, the second material602, and the fin hard mask stack material 210, 212, 214, according tofour example embodiments of the present invention.

According to a first embodiment, the first material 208, 402, 404, 406,408, and the sidewall spacer material 502, 504, are both silicondioxide. The second material is silicon nitride. The top layer 210 ofthe fin hard mask stack includes amorphous silicon.

According to a second embodiment, the first material 208, 402, 404, 406,408, and the sidewall spacer material 502, 504, are both silicondioxide. The second material is transition metal oxides. The transitionmetal may be any one of titanium, tantalum, or tungsten. The top layer210 of the fin hard mask stack includes silicon nitride.

According to a third embodiment, the first material 208, 402, 404, 406,408, and the sidewall spacer material 502, 504, are both silicondioxide. The second material is silicon carbide. The top layer 210 ofthe fin hard mask stack includes amorphous silicon.

According to a fourth embodiment, the first material 208, 402, 404, 406,408, and the sidewall spacer material 502, 504, are both silicondioxide. The second material is silicon carbide. The top layer 210 ofthe fin hard mask stack includes amorphous silicon.

The above discussed fabrication process can be applied to anysemiconductor structure that utilizes very thin lines and wide openspaces between adjacent lines. One example is finFET transistors. Asecond example is vertical transistors, which could be FETs. A thirdexample is vertical metal inter-connects in a back end of the line(BEOL) metallization stack.

According to one example fabrication process for manufacturing verticaltransistors, after the fins 802, 804, 806, 808, separated by wide openspaces 702, are formed, as shown in FIG. 7, the fin hard mask 201, 212,214, and pad oxide 216, would be removed using a form of etch, either adry etch or wet etch. Following that, epitaxy would be used to form thebottom source/drain contacts in the trench 702. In the wide open spacesepitaxy would be used to form the bottom source/drain. On top of that, agate dielectric material would be deposited which would wrap around thesilicon fins 802, 804, 806, 808. On top of that, gate metal would bedeposited which would wrap around the gate dielectric. On top of thatanother epitaxy step would be conducted which would form the topsource/drain of the vertical transistor. This would result infabrication of vertical transistor structures using the fins 802, 804,806, 808.

FIG. 9 illustrates an example method 1000 for fabricating verticaltransistor devices on the same chip. Various embodiments of theinvention may include some, and not necessarily all, of the method stepsin the illustrated example.

The method enters, at step 1002, and immediately proceeds, at step10004, to form layers of materials (layers 204 to 216) on a substrate(218); and then deposit lithography resist (202), and perform toneinverse lithography on a material stack 204, 206, 208, as has beendiscussed above. The tone inverse lithography is a direct printlithography process using extreme ultraviolet light (EUV).

The method then proceeds, at step 1006, to perform vertical directionaletching (dry etch) pattern transfer into materials 204, 206, 208; andthen remove materials 202, 204, 206 by wet etch or isotropic dry etch.

The method then, at step 1008, deposits spacer material 502 and 504selectively on sidewalls of the first material 208 and mandrel 402, 404,406, and 408. This selective deposition can be done using an ALDprocess. The method then performs selective bottom-up trench fill orselective bottom-up gap-fill of material 602; and then performs a dryetch or wet etch of material 402, 404, 406 and 408, to form wide spaces702.

The method, at step 1010, performs vertical directional etching (dryetch) pattern transfer into materials 210, 212, 214, 216, to form finhard mask stacks 801; and then performs vertical directional etching(dry etch) pattern transfer into the substrate 218 to form fins 802,804, 806, 808, 810. The method then removes the fin hard mask stack(materials 210, 212, 214) and the pad oxide layer 216, by wet etch orisotropic dry etch. The method then exits, at step 1012. The fins 802,804, 806, 808, 810, are formed in the semiconductor substrate 218,according to the example fabrication process, in a pattern that providesa combination of low duty cycle (i.e., a duty cycle of 1:5 or lower)with a fin pattern 802, 804, 806, 808, having zero pitch walk (or nearlyzero pitch walk within negligible tolerances).

Although specific embodiments of the invention have been disclosed,those having ordinary skill in the art will understand that changes canbe made to the specific embodiments without departing from the scope ofthe invention. The scope of the invention is not to be restricted,therefore, to the specific embodiments, and it is intended that theappended claims cover any and all such applications, modifications, andembodiments within the scope of the present invention.

It should be noted that some features of the present invention might beused in one embodiment thereof without use of other features of thepresent invention. As such, the foregoing description should beconsidered as merely illustrative of the principles, teachings,examples, and exemplary embodiments of the present invention, and not alimitation thereof.

In addition, these embodiments are only examples of the manyadvantageous uses of the innovative teachings herein. In general,statements made in the specification of the present application do notnecessarily limit any of the various claimed inventions. Moreover, somestatements may apply to some inventive features but not to others.

What is claimed is:
 1. A method for fabricating a pattern of verticalfins in a semiconductor structure, the method comprising: providing asemiconductor material stack including a plurality of layers; andcreating an inverse tone direct print pattern in the semiconductormaterial stack, where a critical dimension of the inverse tone directprint pattern is defined by selective sidewall atomic layer depositionon sidewalls of a mandrel pattern formed by vertical directional etchingin the semiconductor material stack, to create trenches in at least onelayer in the plurality of layers.
 2. The method of claim 1, wherein theselective sidewall atomic layer deposition creates sidewall spacers onsidewalls of the mandrel pattern on a fin hard mask stack.
 3. The methodof claim 1, wherein the inverse tone direct print pattern in thesemiconductor material stack is created by selective bottom-up gap fillin the trenches in the at least one layer in the plurality of layers. 4.The method of claim 1, wherein the semiconductor material stackincludes: a semiconductor substrate layer; a fin hard mask stack,including one or more layers, disposed on the semiconductor substratelayer; a first material layer, consisting of a first material, disposedon the fin hard mask stack; and a photolithography stack, including oneor more layers, disposed on the first material layer; and wherein themethod includes: forming an inverse tone direct print pattern on a toplayer of the photolithography stack using direct print lithography;performing a first vertical directional etching in the photolithographystack and in the first material layer to form a mandrel pattern in thefirst material layer; and performing selective sidewall atomic layerdeposition to create sidewall spacers on sidewalls of the mandrelpattern disposed on the fin hard mask stack.
 5. The method of claim 4,further comprising: performing trench fill with a second material tofill only trenches that were formed between the sidewall spacers onsidewalls of the mandrel pattern; performing etching to remove the firstmaterial, the mandrel pattern, and the sidewall spacers, leaving thesecond material disposed, in a first pattern following a pattern of thetrenches that were formed between the sidewall spacers, on the fin hardmask stack; performing second vertical directional etching in the finhard mask stack and in the semiconductor substrate layer only wherelayers are vertically exposed outside of the first pattern of the secondmaterial disposed on the fin hard mask stack, to form vertical fins in avertical fin pattern in the semiconductor substrate layer; and removing,after the second vertical directional etching, the second material andthe fin hard mask stack, exposing the vertical fins in the vertical finpattern formed in the semiconductor substrate layer.
 6. The method ofclaim 5, wherein the first material comprises silicon dioxide and thesecond material comprises transition metal oxides.
 7. The method ofclaim 6, wherein the transition metal is one of titanium, tantalum, ortungsten.
 8. The method of claim 5, wherein the sidewall spacers on thesidewalls of the mandrel pattern in the first material layer comprisesilicon dioxide.
 9. The method of claim 5, wherein the fin hard maskstack comprises three layers including a silicon nitride layer disposeddirectly on a silicon dioxide layer, and which is disposed directly on asilicon nitride layer.
 10. The method of claim 5, wherein the verticalfins in the vertical fin pattern are separated by wide-open spaces,along a critical dimension, in a low duty cycle of 1:5 or lower.
 11. Themethod of claim 5, wherein the vertical fins in the vertical fin patternare separated by wide-open spaces, along a critical dimension, in a lowduty cycle of 1:5 or lower, and wherein pairs of adjacent vertical finsin the vertical fin pattern, along the critical dimension, are separatedby a constant pitch value at near zero tolerance.
 12. A semiconductorstructure comprising: a plurality of vertical fins in a vertical finpattern, wherein adjacent vertical fins in the vertical fin pattern areall separated by respective wide-open spaces, along a criticaldimension, in a low duty cycle of 1:5 or lower.
 13. The semiconductorstructure of claim 12, wherein pairs of adjacent vertical fins in thevertical fin pattern on a substrate, along the critical dimension, areseparated by a constant pitch value at near zero tolerance.
 14. Thesemiconductor structure of claim 13, wherein the constant pitch value issmaller than 76 nm.
 15. The semiconductor structure of claim 13, whereinthe near zero tolerance is lower than 0.1 nm.
 16. The semiconductorstructure of claim 12, wherein the plurality of vertical fins in avertical fin pattern on a substrate on a semiconductor chip comprise atleast one of: a plurality of vertical fin field-effect transistor(finFET) devices; or a plurality of vertical transistor devices.
 17. Thesemiconductor structure of claim 12, wherein the plurality of verticalfins in a vertical fin pattern on a substrate on a semiconductor chipcomprise a plurality of back-end-of-line vertical metallizationstructures.
 18. A method for fabricating a pattern of vertical fins in asemiconductor structure, the method comprising: providing asemiconductor material stack including a plurality of layers directly ona semiconductor substrate layer; forming an inverse tone direct printpattern in the semiconductor material stack; performing verticaldirectional etching according to the inverse tone direct print patternto form vertical fins in a vertical fin pattern in the semiconductorsubstrate layer, wherein the vertical fins in the vertical fin patternare separated by wide-open spaces, along a critical dimension, in a lowduty cycle of 1:5 or lower.
 19. The method of claim 18, wherein pairs ofadjacent vertical fins in the vertical fin pattern, along the criticaldimension, are separated by a constant pitch value at near zerotolerance.
 20. The method of claim 19, wherein the constant pitch valueis smaller than 76 nm, and the near zero tolerance is lower than 0.1 nm.